The present invention relates generally to clocking of communication circuits, and more particularly to a method for switching master/slave timing in a data communication link, for example, a 1000BASE-T link, without disrupting data traffic on the link.
Devices for communication over a data link often include transmit and receive circuits termed PHYs. PHYs used in loop-timed systems, such as 1000BASE-T Ethernet, operate as either masters or slaves. The PHY at one end of a data link operates as a master and the PHY at the other end operates as a slave. With respect to signal timing, the PHY operating as a master transmits a signal using a reference clock signal for timing, and the PHY operating as a slave transmits a signal using a clock signal recovered from the signal received from the master. Other operational characteristics of the PHYs may also depend on whether a PHY is a master or a slave. For example, a polynomial used for data scrambling in a 1000BASE-T link may have different values in a master than in a slave. Which end of the data link is the master is commonly determined when the link is initialized, for example, using an auto-negotiation process. The auto-negotiation process may take several seconds and during the process generally no payload data is exchanged. Thus, reassignment of the timing master in a data link is generally highly disruptive to data communication on the link.